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White Electronic Designs
2Mx32 5V Flash Module
FEATURES
Access Time of 90, 120, 150ns Packaging: * 66 pin, PGA Type, 1.185" square, Hermetic Ceramic HIP (Package 401). * 68 lead, Hermetic CQFP (G2U), 22.4mm (0.880") square (Package 510) 3.56mm (0.140") height. Designed to fit JEDEC 68 lead 0.990" CQFJ footprint (FIGURE 3) Sector Architecture * 32 equal size sectors of 64KBytes per each 2Mx8 chip * Any combination of sectors can be erased. Also supports full chip erase. Minimum 100,000 Write/Erase Cycles Minimum Organized as 2Mx32
WF2M32-XXX5
Commercial, Industrial, and Military Temperature Ranges 5 Volt Read and Write. 5V 10% Supply. Low Power CMOS Data# Polling and Toggle Bit feature for detection of program or erase cycle completion. Supports reading or programming data to a sector not being erased. RESET# pin resets internal state machine to the read mode. Built in Decoupling Caps and Multiple Ground Pins for Low Noise Operation, Separate Power and Ground Planes to improve noise immunity
* This product is subject to change without notice. Note: For programming information refer to Flash Programming 16M5 Application Note.
FIGURE 1 - PIN CONFIGURATION FOR WF2M32-XHX5 Top View
1 I/O8 I/O9 I/O10 A14 A16 A11 A0 A18 I/O0 I/O1 I/O2 11 22 12 WE2# CS2# GND I/O11 A10 A9 A15 VCC CS1# A19 I/O3 33 23 I/O15 I/O14 I/O13 I/O12 OE# A17 WE1# I/O7 I/O6 I/O5 I/O4 I/O24 I/O25 I/O26 A7 A12 A20 A13 A8 I/O16 I/O17 I/O18 44 34 VCC CS4# WE4# I/O27 A4 A5 A6 WE3# CS3# GND I/O19 55 45 I/O31 I/O30 I/O29 I/O28 A1 A2
OE# A0-20
Pin Description
56
I/O0-31 A0-20 WE1-4# CS1-4# OE# VCC GND
Data Inputs/Outputs Address Inputs Write Enables Chip Selects Output Enable Power Supply Ground
Block Diagram
WE1# CS1# WE2# CS2# WE3# CS3# WE4# CS4#
A3
2M x 8 2M x 8 2M x 8 2M x 8
I/O23 I/O22 I/O21 I/O20 66
8 8 8 8
I/O0-7
I/O8-15
I/O16-23
I/O24-31
RESET# internally tied to VCC in the HIP package for this pin configuration. See Alternate Pin Configuration with RESET# tied to pin 12 for system control of reset (FIGURE 10, page 11).
October 2004 Rev. 5
1
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White Electronic Designs
WF2M32-XXX5
FIGURE 2 - PIN CONFIGURATION FOR WF2M32-XG2UX5
Top View
RESET# A0 A1 A2 A3 A4 A5 CS3# GND CS4# WE1# A6 A7 A8 A9 A10 VCC
Pin Description
I/O0-31 A0-20 WE1-4# CS1-4# OE# VCC GND RESET# Data Inputs/Outputs Address Inputs Write Enables Chip Selects Output Enable Power Supply Ground Reset
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 GND I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 GND I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31
Block Diagram
WE1# CS1# RESET# OE# A0-20 2M x 8 2M x 8 WE2# CS2# WE3# CS3# WE4# CS4#
VCC A11 A12 A13 A14 A15 A16 CS1# OE# CS2# A17 WE2# WE3# WE4# A18 A19 A20
2M x 8
2M x 8
8
8
8
8
I/O0-7
I/O8-15
I/O16-23
I/O24-31
The WEDC 68 lead G2U CQFP fills the same fit and function as the JEDEC 68 lead CQFJ or 68 PLCC. But the G2U has the TCE and lead inspection advantage of the CQFP form.
0.940"
October 2004 Rev. 5
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ABSOLUTE MAXIMUM RATINGS
Parameter Voltage on Any Pin Relative to VSS Power Dissipation Storage Temperature Short Circuit Output Current Endurance - Write/Erase Cycles (Extended Temp) Data Retention Symbol VT PT Tstg IOS Ratings -2.0 to +7.0 8 -65 to +125 100 100,000 min 20 Unit V W C mA cycles years
WF2M32-XXX5
CAPACITANCE
TA = +25C, f = 1.0MHz Parameter OE# capacitance WE1-4# capacitance HIP (PGA) HIP (Alternate pinout) CQFP G4T CQFP G2U G2U (Alternate pinout) CS1-4# capacitance Data I/O capacitance Address input capacitance Symbol COE CWE CWE CWE CWE CWE CCS CI/O CAD Max 50 20 50 50 20 50 20 20 50 Unit pF pF pF pF pF pF pF pF pF
This parameter is guaranteed by design but not tested.
RECOMMENDED DC OPERATING CONDITIONS
Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Operating Temperature (Mil.) Operating Temperature (Ind.) Symbol Min VCC VSS VIH VIL TA TA 4.5 0 2.0 -0.5 -55 -40 Typ 5.0 0 Max 5.5 0 VCC + 0.5 +0.8 +125 +85 Unit V V V V C C
DC CHARACTERISTICS - CMOS COMPATIBLE
VCC = 5.0V, VSS = 0V, -55C TA +125C Parameter Input Leakage Current Output Leakage Current VCC Active Current for Read (1) VCC Active Current for Program or Erase (2) VCC Standby Current Output Low Voltage Output High Voltage Low VCC Lock-Out Voltage Symbol ILI ILOx32 ICC1 ICC2 ICC3 VOL VOH VLKO Conditions VCC = 5.5, VIN = GND to VCC VCC = 5.5, VIN = GND to VCC CS# = VIL, OE# = VIH, f = 5MHz CS# = VIL, OE# = VIH VCC = 5.5, CS# = VIH, f = 5MHz, RESET# = VCC 0.3V IOL = 12.0 mA, VCC = 4.5 IOH = -2.5 mA, VCC = 4.5 Min Max 10 10 160 240 8.0 0.45 4.2 Unit A A mA mA mA V V V
0.85xVCC 3.2
NOTES: 1. The ICC current listed includes both the DC operating current and the frequency dependent component (@ 5MHz). The frequency component typically is less than 2mA/MHz, with OE# at VIH. 2. ICC active while Embedded Algorithm (program or erase) is in progress. 3. DC test conditions VIL = 0.3V, VIH = VCC - 0.3V
October 2004 Rev. 5
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VCC = 5.0V, -55C TA +125C Parameter Write Cycle Time Chip Select Setup Time Write Enable Pulse Width Address Setup Time Data Setup Time Data Hold Time Address Hold Time Write Enable Pulse Width High Duration of Byte Programming Operation (1) Sector Erase (2) Read Recovery Time before Write VCC Setup Time Chip Programming Time Chip Erase Time (3) Output Enable Hold Time (4) RESET# Pulse Width (5) Symbol tAVAV tELWL tWLWH tAVWL tDVWH tWHDX tWLAX tWHWL tWHWH1 tWHWH2 tGHWL tVCS tWC tCS tWP tAS tDS tDH tAH tWPH Min 90 0 45 0 45 0 45 20 -90 Max Min 120 0 50 0 50 0 50 20 -120 Max
WF2M32-XXX5
AC CHARACTERISTICS - WRITE/ERASE/PROGRAM OPERATIONS - WE# CONTROLLED
-150 Min 150 0 50 0 50 0 50 20 Max ns ns ns ns ns ns ns ns s sec s s sec sec ns ns Unit
300 15 0 50 44 256 tOEH tRP 10 500 10 500 0 50
300 15 0 50 44 256 10 500
300 15
44 256
NOTES: 1. Typical value for tWHWH1 is 7s. 2. Typical value for tWHWH2 is 1sec. 3. Typical value for Chip Erase Time is 32sec. 4. For Toggle and Data Polling. 5. RESET# internally tied to VCC for the default pin configuration in the HIP package.
AC CHARACTERISTICS - READ-ONLY OPERATIONS
VCC = 5.0V, -55C TA +125C Parameter Read Cycle Time Address Access Time Chip Select Access Time Output Enable to Output Valid Chip Select High to Output High Z (1) Output Enable High to Output High Z (1) Output Hold from Addresses, CS# or OE# Change, whichever is First RST Low to Read Mode (1,2) Symbol tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ tAXQX tRC tACC tCE tOE tDF tDF tOH tReady Min 90 -90 Max 90 90 40 20 20 0 20 0 20 Min 120 -120 Max 120 120 50 30 30 0 20 Min 150 -150 Max 150 150 55 35 35 Unit ns ns ns ns ns ns ns s
NOTES: 1. Guaranteed by design, not tested. 2. RESET# internally tied to VCC for the default pin configuration in the HIP package.
October 2004 Rev. 5
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VCC = 5.0V, VSS = 0V, -55C TA +125C Parameter Write Cycle Time Write Enable Setup Time Chip Select Pulse Width Address Setup Time Data Setup Time Data Hold Time Address Hold Time Chip Select Pulse Width High Duration of Byte Programming Operation (1) Sector Erase Time (2) Read Recovery Time Chip Programming Time Chip Erase Time (3) Output Enable Hold Time (4)
NOTES: 1. Typical value for tWHWH1 is 7s. 2. Typical value for tWHWH2 is 1sec. 3. Typical value for Chip Erase Time is 32sec. 4. For Toggle and Data Polling.
WF2M32-XXX5
AC CHARACTERISTICS - WRITE/ERASE/PROGRAM OPERATIONS,CS# CONTROLLED
Symbol tAVAV tWLEL tELEH tAVEL tDVEH tEHDX tELAX tEHEL tWHWH1 tWHWH2 tGHEL tWC tWS tCP tAS tDS tDH tAH tCPH Min 90 0 45 0 45 0 45 20 -90 Max Min 120 0 50 0 50 0 50 20 -120 Max Min 150 0 50 0 50 0 50 20 -150 Max ns ns ns ns ns ns ns ns s sec s sec sec ns Unit
300 15 0 44 256 tOEH 10 10 0
300 15 0 44 256 10
300 15 44 256
FIGURE 3 - AC TEST CIRCUIT
AC TEST CONDITIONS
IOL Current Source
Parameter Input Pulse Levels Input Rise and Fall Input and Output Reference Level Output Timing Reference Level
Typ VIL = 0, VIH = 3.0 5 1.5 1.5
Unit V ns V V
D.U.T. Ceff = 50 pf
VZ 1.5V (Bipolar Supply)
IOH Current Source
Notes: VZ is programmable from -2V to +7V. IOL & IOH programmable from 0 to 16mA. Tester Impedance Z0 = 75 y. VZ is typically the midpoint of VOH and VOL. IOL & IOH are adjusted to simulate a typical resistive load circuit. ATE tester includes jig capacitance.
FIGURE 4 - RESET TIMING DIAGRAM
RESET#
tRP tReady
October 2004 Rev. 5
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WF2M32-XXX5
FIGURE 5 - AC WAVEFORMS FOR READ OPERATIONS
OE#
October 2004 Rev. 5
6
WE#
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CS#
White Electronic Designs
WF2M32-XXX5
FIGURE 6 - WRITE/ERASE/PROGRAM OPERATION, WE# CONTROLLED
Data# Polling
OE#
CS#
NOTES: 1. PA is the address of the memory location to be programmed. 2. PD is the data to be programmed at byte address. 3. D7# is the output of the complement of the data written to each chip.
4. 5.
DOUT is the output of the data written to the device. Figure indicates last two bus cycles of four bus cycle sequence.
October 2004 Rev. 5
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WE#
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D7#
White Electronic Designs
WF2M32-XXX5
FIGURE 7 - AC WAVEFORMS CHIP/SECTOR ERASE OPERATIONS
OE#
NOTE: 1. SA is the sector address for Sector Erase.
October 2004 Rev. 5
8
WE#
CS#
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WF2M32-XXX5
FIGURE 8 - AC WAVEFORMS FOR DATA# POLLING DURING EMBEDDED ALGORITHM OPERATIONS
tDF
tOH
High Z
D7 = Valid Data
tCH
tOEH
tCE
tWHWH 1 or 2 Data
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tOE
OE#
October 2004 Rev. 5
WE#
CS#
9
D0-D6
D7
D0-D6 = Invalid
D7#
D0-D7 Valid Data
White Electronic Designs
WF2M32-XXX5
FIGURE 9 - ALTERNATE CS# CONTROLLED PROGRAMMING OPERATION TIMINGS
Data# Polling
tGHEL
tCP
OE#
Notes: 1. PA represents the address of the memory location to be programmed. 2. PD represents the data to be programmed at byte address. 3. D7# is the output of the complement of the data written to each chip. 4. DOUT is the output of the data written to the device. 5. Figure indicates the last two bus cycles of a four bus cycle sequence.
October 2004 Rev. 5
10
WE#
CS#
tWS
tCPH
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D7#
White Electronic Designs
WF2M32-XXX5
FIGURE 10 - ALTERNATE PIN CONFIGURATION FOR WF2M32I-XHX5
TOP VIEW
1 I/O8 I/O9 I/O10 A14 A16 A11 A0 A18 I/O0 I/O1 I/O2 11 22 12 RESET# CS2# GND I/O11 A10 A9 A15 VCC CS1# A19 I/O3 33 23 I/O15 I/O14 I/O13 I/O12 OE# A17 WE# I/O7 I/O6 I/O5 I/O4 I/O24 I/O25 I/O26 A7 A12 NC A13 A8 I/O16 I/O17 I/O18 44 34 VCC CS4# NC I/O27 A4 A5 A6 A20 CS3# GND I/O19 55 45 I/O31 I/O30 I/O29 I/O28 A1 A2 A3 I/O23 I/O22
2M x 8 2M x 8 2M x 8 2M x 8 RESET# WE# OE# A0-20
PIN DESCRIPTION
56
I/O0-31 A0-20 WE# CS1-4# OE# VCC GND RESET#
Data Inputs/Outputs Address Inputs Write Enable Chip Selects Output Enable Power Supply Ground Reset
BLOCK DIAGRAM
CS1# CS2# CS3# CS4#
I/O21
8 8 8 8
I/O20 66
I/O0-7 I/O8-15 I/O16-23 I/O24-31
FIGURE 11 - ALTERNATE PIN CONFIGURATION FOR WF2M32U-XG2UX5
TOP VIEW
RESET# A0 A1 A2 A3 A4 A5 NC GND NC WE# A6 A7 A8 A9 A10 VCC
PIN DESCRIPTION
I/O0-31 A0-20 WE# CS# OE# VCC GND RESET# Data Inputs/Outputs Address Inputs Write Enable Chip Select Output Enable Power Supply Ground Reset
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 GND I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 GND I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31
0.940"
The WEDC 68 lead G2U CQFP fills the same fit and function as the JEDEC 68 lead CQFJ or 68 PLCC. But the G2U has the TCE and lead inspection advantage of the CQFP form.
BLOCK DIAGRAM
RESET# CS# WE# OE# A0-20 2M x 8 2M x 8
VCC A11 A12 A13 A14 A15 A16 CS# OE# NC A17 NC NC NC A18 A19 A20
2M x 8
2M x 8
8
8
8
8
I/O0-7
I/O8-15
I/O16-23
I/O24-31
October 2004 Rev. 5
11
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WF2M32-XXX5
FIGURE 12 - PIN CONFIGURATION FOR WF2M32I-XG2UX5
TOP VIEW
RESET# A0 A1 A2 A3 A4 A5 CS3# GND CS4# WE# A6 A7 A8 A9 A10 VCC
PIN DESCRIPTION
I/O0-31 A0-20 WE# CS1-4# OE# VCC GND RESET# Data Inputs/Outputs Address Inputs Write Enable Chip Selects Output Enable Power Supply Ground Reset
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 GND I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 GND I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31
BLOCK DIAGRAM
CS1# RESET# WE# OE# A0-20 CS2# CS3# CS4#
2M x 8
2M x 8
2M x 8
2M x 8
VCC A11 A12 A13 A14 A15 A16 CS1# OE# CS2# A17 NC NC NC A18 A19 A20
8
8
8
8
I/O0-7
I/O8-15
I/O16-23
I/O24-31
The WEDC 68 lead G2U CQFP fills the same fit and function as the JEDEC 68 lead CQFJ or 68 PLCC. But the G2U has the TCE and lead inspection advantage of the CQFP form.
0.940"
October 2004 Rev. 5
12
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White Electronic Designs
WF2M32-XXX5
PACKAGE 401: 66 PIN, PGA TYPE, CERAMIC HEX-IN-LINE PACKAGE, HIP (H)
30.1 (1.185) 0.38 (0.015) SQ
PIN 1 IDENTIFIER SQUARE PAD ON BOTTOM
25.4 (1.0) TYP
6.22 (0.245) MAX 3.81 (0.150) 0.1 (0.005) 2.54 (0.100) TYP 1.27 (0.050) 0.1 (0.005) 0.76 (0.030) 0.1 (0.005) 15.24 (0.600) TYP 1.27 (0.050) TYP DIA 0.46 (0.018) 0.05 (0.002) DIA 25.4 (1.0) TYP
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
October 2004 Rev. 5
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WF2M32-XXX5
PACKAGE 510: 68 LEAD, CERAMIC QUAD FLAT PACK, CQFP (G2U)
The WEDC 68 lead G2U CQFP fills the same fit and function as the JEDEC 68 lead CQFJ or 68 PLCC. But the G2U has the TCE and lead inspection advantage of the CQFP form.
0.940" TYP
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
October 2004 Rev. 5
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ORDERING INFORMATION
WF2M32-XXX5
W F 2M32 X - XXX X X 5 X
LEAD FINISH: Blank = Gold plated leads A = Solder dip leads VPP PROGRAMMING VOLTAGE 5=5V DEVICE GRADE: Q = Compliant -55C to +125C M = Military -55C to +125C I = Industrial -40C to +85C C = Commercial 0C to +70C PACKAGE TYPE: H = Ceramic Hex In line Package, HIP (Package 401) G2U = 22.4mm Ceramic Quad Flat Pack, CQFP (Package 510) ACCESS TIME (ns) IMPROVEMENT MARK * For HIP Package Blank = 4CS# and 4WE# I = 4CS# and 1WE#, RESET# * For G2U Package Blank = 4CS# and 4WE# U = 1CS# and 1WE# I = 4CS# and 1WE#, RESET# ORGANIZATION, 2M x 32 User configurable as 4M x 16 or 8M x 8 (Except WF2M32U-XG2UX which is 32 bit wide only.) Flash WHITE ELECTRONIC DESIGNS CORP.
October 2004 Rev. 5
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